page 1 of 7 document no. 70-0119-02 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. the PE9312 is a high-performance static ultracmos? prescaler with a fixed divide ratio of 4. its operating frequency range is dc to 1500 mhz. the PE9312 operates on a nominal 3 v supply and draws only 6.5 ma. it is packaged in a small 8-lead ceramic soic and is ideal for frequency scaling and clock generation solutions. the PE9312 is manufactured in peregrine?s patented ultra- thin silicon (utsi ? ) cmos process, offering the performance of gaas with the economy and integration of conventional cmos. product description figure 1. functional diagram features ? dc to 1500 mhz operation ? fixed divide ratio of 4 ? low-power operation: 6.5 ma typical @ 3 v ? ultra small package: 8-lead ceramic soic ? guaranteed 100 krads(si) total dose performance ? superior single event upset immunity table 1. electrical specifications @ +25 c, v dd = 2.6 v (z s = z l = 50 ? ) parameter conditions minimum typical maximum units supply voltage 2.85 3.0 3.15 v supply current 6.5 11 ma input frequency (f in ) dc 1500 mhz input power (p in ) dc < fin ? 1000 mhz -8 +10 dbm 1000 < fin ? 1500 mhz 0 +10 dbm output power (p out ) dc < fin ? 1500 mhz 0 dbm v dd = 3.0 v, -40 c t a 85 c, unless otherwise specified d qb q clk d qb q clk pre-amp output buffer in out product specification PE9312 1500 mhz low power ultracmos? divide-by-4 prescaler rad hard for space applications figure 2. package type 8-lead csoic
product specification PE9312 page 2 of 7 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0119-02 ultracmos? rfic solutions table 2. pin descriptions table 3. absolute maximum ratings device functional considerations the PE9312 divides an input signal, up to a frequency of 1500 mhz, by a factor of four thereby producing an output frequency at a quarter of the input frequency. to work properly at higher frequency, the input and output signals (pins 2 & 7) must be ac coupled via an external capacitor, as shown in the test circuit in figure 8. the input may be dc coupled for low frequency operation with care taken to remain within the specified dc input range for the device. the ground pattern on the board should be made as wide as possible to minimize ground impedance. see figure 7 for a layout example. latch-up avoidance unlike conventional cmos devices, ultracmos? devices are immune to latch-up. figure 3. pin configuration electrostatic discharge (esd) precautions when handling this ultracmos? device, observe the same precautions that you would use with other esd-sensitive devices. although this device contains circuitry to protect it from damage due to esd, precautions should be taken to avoid exceeding the rating specified in table 3. PE9312 1 2 3 4 8 7 6 5 in gnd n/c gnd out v dd nc gnd pin no. pin name description 1 v dd power supply pin. bypassing is required (eg 1000 pf & 100 pf). 2 in input signal pin. should be coupled with a capacitor (eg 1000 pf). 3 nc no connection. this pin should be left open. 4 gnd ground pin. ground pattern on the board should be as wide as possible to reduce ground impedance. 5 gnd ground pin. 6 nc no connection. this pin should be left open. 7 out divided frequency output pin. this pin should be coupled with a capacitor (eg 1000 pf). 8 gnd ground pin. symbol parameter/conditions min max units v dd supply voltage 4.0 v p in input power 15 dbm v in voltage on input -0.3 v dd +0.3 v t st storage temperature range -65 150 c t op operating temperature range -40 85 c v esd esd voltage (human body model, mil-std 883) 1000 v absolute maximum rati ngs are those values listed in the above table. exceeding these values may cause permanent device damage. functional operation should be restricted to the limits in the dc electrical specifications table. exposure to absolute maximum ratings for extended periods may affect device reliability.
product specification PE9312 page 3 of 7 document no. 70-0119-02 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. typical performance data: v dd = 3.0 v figure 4. input sensitivity figure 5. device current figure 6. output power
product specification PE9312 page 4 of 7 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0119-02 ultracmos? rfic solutions figure 7. test circuit block diagram 50 vdd in n/c gnd gnd out n/c gnd 1000 pf 100 pf 1000pf 1000pf 3 v power meter or frequency counter 50
product specification PE9312 page 5 of 7 document no. 70-0119-02 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. evaluation kit operation the ceramic soic prescaler evaluation board was designed to help customers evaluate the PE9312 divide-by-2 prescaler. on this board, the device input (pin 2) is connected to the sma connector j1 through a 50 ? transmission line. a series capacitor (c3) provides the necessary dc block for the device input. a value of 1000 pf was used for the evaluation board; other applications may require a different value. it is also possible to place a 0 ? resistor in this location for very low frequency applications. the device output (pin 7) is connected to sma connector j3 through a 50 ? transmission line. a series capacitor (c1) provides the necessary dc block for the device output. this capacitor value must be chosen to have a low impedance at the desired output frequency of the device. a value of 1000 pf was chosen for the evaluation board. the board is constructed of a two-layer fr4 material with a total thickness of 0.031?. the bottom layer provides ground for the rf transmission lines. the transmission lines were designed using a coplanar waveguide above ground plane model with trace width of 0.030?, trace gaps of 0.0061?, dielectric thickness of 0.028?, metal thickness of 0.0014?, and r of 4.6. note that the predominate mode of these transmission lines is coplanar waveguide. j2 provides dc power to the device via pin 1. two decoupling capacitors (c2=100 pf, c10=1000 pf) are included on this trace. it is the responsibility of the customer to determine proper supply decoupling for their design application. figure 8. evaluation board layout figure 9. evaluation board schematic peregrine specification 102/0202 peregrine specification 102/0034
product specification PE9312 page 6 of 7 ?2005 peregrine semiconductor corp. all rights reserved. document no. 70-0119-02 ultracmos? rfic solutions top view .050 typ .015 typ .150 typ .380 / .410 .210 / .250 .180 sq max pin 1 side view .070 max table 4. ordering information order code part marking description package shipping method 9312-01 PE9312 PE9312-08cfpg-b engineering samples gullwing glass flatpack 50 / tray 9312-11 PE9312 PE9312-08cfpg-b production units gullwing glass flatpack 50 / tray 9312-00 PE9312-ek PE9312 evaluation kit evaluation kit 1 / box 8-lead csoic figure 10. package drawing
product specification PE9312 page 7 of 7 document no. 70-0119-02 www.psemi.com ?2005 peregrine semiconductor corp. all rights reserved. sales offices the americas peregrine semiconductor corp. 9450 carroll park drive san diego, ca 92121 tel 858-731-9400 fax 858-731-9499 north asia pacific peregrine semiconductor k.k. 5a-5, 5f imperial tower 1-1-1 uchisaiwaicho, chiyoda-ku tokyo 100-0011 japan tel: +81-3-3502-5211 fax: +81-3-3502-5213 europe peregrine semiconductor europe commercial products: batiment maine 13-15 rue des quatre vents f- 92380 garches, france tel: +33-1-47-41-91-73 fax : +33-1-47-41-91-73 space and defense products: 180 rue jean de guiramand 13852 aix-en-provence cedex 3, france tel: +33(0) 4 4239 3361 fax: +33(0) 4 4239 7227 for a list of representatives in your area, please refer to our web site at: www.psemi.com data sheet identification advance information the product is in a formative or design stage. the data sheet contains design target specifications for product development. specifications and features may change in any manner without notice. preliminary specification the data sheet contains preliminary data. additional data may be added at a later date. peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. product specification the data sheet contains final data. in the event peregrine decides to change the specifications, peregrine will notify customers of the intended changes by issuing a dcn (document change notice). the information in this data sheet is believed to be reliable. however, peregrine assumes no liability for the use of this information. use shall be entirely at the user?s own risk. no patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. peregrine?s products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the peregrine product could create a situation in which personal injury or death might occur. peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. the peregrine name, logo, and utsi are registered trademarks and ultracmos is a trademark of peregrine semiconductor corp. south asia pacific peregrine semiconductor 28g, times square, no. 500 zhangyang road, shanghai, 200122, p.r. china tel: +86-21-5836-8276 fax: +86-21-5836-7652
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